In ALL these modules (7164, 7166, 7167, 7186* and 7187),
digitization may be delayed by an amount from 0 to 16us in 62.5ns increments
using the "Conversion Delay" jumpers at the rear of the module.
This will allow a greater acceptance window for CLEAR signals if needed.
Once digitization begins, you will not be able to clear or access
the module until the conversion cycle has been completed.
600ns after the trailing edge of the Gate signal.
|QDC 7166, 7167
750ns after the trailing edge of the Gate signal
|TDC 7186, 7187
750ns after the leading edge of the COMMON pulse
for the 7186, and 750ns after the trailing edge of the Gate pulse for the 7187
The 600ns and 750ns delay before starting the Conversions
is for settling time and also allows time to accept fast clear signals.
*7186 COMMON START ONLY
It is recommended to delay digitization for the 7186 TDC when using COMMON START mode above 100ns full scale. This prevents the module from beginning the Conversion Cycle to early. It allows settling time and a few hundred nanoseconds for a fast clear acceptance window.
Example: If the module is set for 2us Full Scale with no additional delay, after 750ns from the Common Pulse (START), digitization begins. The module switches to "Hold" mode before Full Scale is reached therefore the highest reading you could get is around 750ns instead of 2us, This would also happen in channels with no stop pulses. The Manual shows the minimum recommended delays for the various Full Scale ranges when used in COMMON START mode. The chart is repeated here. Note: The COMMON STOP mode does not require this.
- 100 nsec)
Back to Technical Questions